Over the past 12 months, Intel has slowly started to disclose information about its first hybrid x86 platform, Lakefield. This new processor combines one ‘big’ CPU core with four ‘small’ CPU cores, along with a hefty chunk of graphics, with Intel setting out to deliver a new computing form factor. Highlights for this processor include its small footprint, due to new 3D stacking ‘Foveros’ technology, as well as its low standby SoC power, as low as 2.5 mW, which Intel states is 91% lower than previous low power Intel processors. Today’s announcement comes in two parts: first, the specifications.

Intel will debut these two SKUs in its first generation of Lakefield. These CPUs will find homes in premium, always-connected laptops, such as the Samsung Galaxy Book S expected in markets this month, the Lenovo ThinkPad X1 Fold, coming later this year, and in the Microsoft Surface Book Neo.

Both SKUs will feature one big ‘Sunny Cove’ CPU core, along with four little ‘Tremont’ Atom CPU cores. Both sets of cores will have access to a 4 MB last level cache, although Intel has not yet disclosed what sort of cache this is.

Meanwhile on the graphics front, Intel is integrating a Gen11 GPU with 64 execution units, the same number of EUs as on Intel's Ice Lake processors. Interestingly, the iGPU is clocked about half as high as usual for an Intel GPU, with clockspeeds peaking at just 500 MHz – suggesting that Intel is going wide and slow to increase graphics performance. Both CPUs will be rated for a TDP of 7 W.

Intel Lakefield Processors
AnandTech Cores Base
Freq
1C
Turbo
nT
Turbo
Gen11
IGP
IGP
Freq
DRAM
LP4
TDP
i5-L16G7 1+4 1400 3000 1800 64 EUs 500 4267 7 W
i3-L13G4 1+4 800 2800 1300 48 EUs 500 4267 7 W

Intel confirmed to us that the base frequency is the unified frequency across all five cores, and the single core turbo frequency applies only to the big Sunny Cove core. Support for LPDDR4X-4266 is a notch above the memory controller in Ice Lake, which only runs at LPDDR4X-3733, and the memory speed will likely be a big boost to performance.

In order to enable these processors in a small 12mm x 12mm footprint, Intel is using its 3D stacking technology, called Foveros. This means that the logic areas of the chip, such as the cores and the graphics, sit on a 10+ nm die, while the IO parts of the chip are on a 22nm silicon die, and they are stacked together. In order to make the connections work, Intel has enabled 50 micron connection pads between the two silicon halves, along with power-focused TSVs (through silicon vias) in order to power the cores on the top layer.

Intel lists the TDP for these chips at 7 W, although the company has not disclosed the turbo power limits for the chip. As mentioned above, Intel hasn’t disclosed how the cache works. In the initial diagrams, we were shown that PoP memory would be added on top, and while Intel hasn't offered further details there, we know from last month's Samsung Galaxy Book S reveal that there will be (at least) 8GB SKUs using LPDDR4X.

We have big questions as to how each of the cores will work, given that by default they support different instruction sets – Intel hasn’t provided information on this at this time. Intel has stated that the scheduling of the threads on the different parts of the CPU will occur based on hardware-guided OS scheduling, although again Intel hasn’t gone into the details of its hardware tracking and enablement on how this is done. In the demos we have seen, Lakefield will use the Tremont cores for almost everything, and only call on the Sunny Cove core for user-experience type of interactions, such as typing or interacting with the screen.


Lenovo ThinkPad X1 Fold

Intel is planning a post-announcement briefing for press to ask questions, which means that this announcement is coming in two parts. This is the information we’re being given beforehand, and we will update you with the details from the post-announcement briefing. As part of this process, we’ve exclaimed to Intel how this way around of presenting details to the press is frustrating – firstly for readers, as you all will have to come back if you want to find out what more Intel tells us later today, but secondly for us, as press, who will have to scramble to jump on the details and decide whether to write fast and miss details, or write slow and miss the wave of traffic.

One thing we can confirm in advance – the Sunny Cove does not appear to be AVX-512 enabled. Intel’s initial press release states that AI workloads occur on the CPU; given the extra power draw required for AVX-512, this is probably a good thing.

More information out of Intel’s post-announcement press-briefing will come later today.

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  • IntelUser2000 - Wednesday, June 10, 2020 - link

    The original in-order Atoms had Hyperthreading but they were so slow it didn't matter. Intel ditched it with the out of order Atoms. They were decent enough to use. Reply
  • trivik12 - Wednesday, June 10, 2020 - link

    I hope Anandtech does review Samsung Galaxy Book s which is available to order in some countries to be shipped early July. I hope press gets hold of these devices early. I am curious if its efficient enough for Surface Neo factor. We dont have a date for that yet right? Reply
  • lmcd - Wednesday, June 10, 2020 - link

    Later than 2020 at minimum. Reply
  • zmatt - Wednesday, June 10, 2020 - link

    "Lakefield" is a very oldschool sounding name. Maybe I've just gotten used to everything they make follow the -lake formula for the last four years but calling it Lakefield instead of the obvious Fieldlake (lol) reminds me of something from the early Core era Like Bloomfield and Yorkfield. Reply
  • Oxford Guy - Wednesday, June 10, 2020 - link

    7 W, eh?

    Is that real-world or "Intel TDP math"?
    Reply
  • Spunjji - Tuesday, June 16, 2020 - link

    I'm betting that's just code running on the 4 small cores and a bit of GPU activity. That Sunny Cove core at full turbo can use 3W all by itself. Reply
  • abufrejoval - Wednesday, June 10, 2020 - link

    I'd certainly pay €150 for these vs the J5005 on the €99 ASrock mainboards I am using now (among many others).

    But Intel wants premium money for these with 8GB max DRAM, while I am putting 32GB of RAM on the J5005 (tested 48GB yesterday to see if 64GB would work, but it doesn't seem to like 32GB sticks).

    I see these competing with a Jetson Nano, another €99 buy, which kicks some serious GPU ass at similar Wattage while several process nodes older.

    Too little for too much, it will break their neck. Apple seems able to do that, but they have a captive clientele, the rest of us enjoy choice too much to follow either of the two.

    Mind you, Qualcom deserves some competition and I'm more than a little sad I can't have a Kirin 990 for €99 on a Mini-ITX or in a clamshell.
    Reply
  • lmcd - Wednesday, June 10, 2020 - link

    It's not like the presence of Lakefield prevents Intel from releasing an Atom-only product as you're describing. But the whole point of Lakefield is the PoP package, so you can't expect the product you're describing re: ITX form factor.

    As an expensive SBC, it could work. There aren't that many choices for a small device with widespread distribution compatibility. It'd be pleasant for virtualization, especially if the iGPU can be virtualized like many Intel iGPUs can.
    Reply
  • trivik12 - Wednesday, June 10, 2020 - link

    One question is why is intel releasing lakefield with sunnycove when Tigerlake with willow cove is around the corner and is supposedly way more efficient. Couldn't intel update Lakefiled to use willow cove core with tremont.

    I hope there is a plan for Gen 2 with Golden Cove and next gen Atom(Gracemont).
    Reply
  • brantron - Thursday, June 11, 2020 - link

    Tiger Lake has larger caches, so may not fit in the dinky package.

    It's also tuned for higher clocks, so higher leakage. Note that Intel's 14nm low TDP CPUs do not use the ++++++++++ or whatever it is now.
    Reply

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