HBM

High-performance computing chip designs have been pushing the ultra-high-end packaging technologies to their limits in the recent years. A solution to the need for extreme bandwidth requirements in the industry has been the shifts towards large designs integrated into silicon interposers, directly connected to high-bandwidth-memory (HBM) stacks. TSMC has been evolving their CoWoS-S packaging technology over the years, enabling designers to create bigger and beefier designs with bigger logic dies, and more and more HBM stacks. One limitation for such complex designs has been the reticle limit of lithography tools. Recently, TSMC has been increasing their interpose size limitation, going from 1.5x to 2x to even projected 3x reticle sizes with up to 8 HBM stacks for 2021 products. As part of TSMC’s 2020 Technology Symposium, the...

AMD Dives Deep On High Bandwidth Memory - What Will HBM Bring AMD?

Earlier this month at AMD’s 2015 Financial Analyst day, the company announced that they would be releasing their first High Bandwidth Memory-equipped GPU – the world’s first HBM-equipped GPU...

163 by Ryan Smith on 5/19/2015

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