At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the form of N5P and N4 process nodes.

Starting off with TSMC’s upcoming N5 process node which represents its 2nd generation deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) process node after the rarely used N7+ node (Used by the Kirin 990 SoC for example). TSMC has been in mass production for several months now as we’re expecting silicon shipping to customers at this moment with consumer products shipping this year – Apple’s next-generation SoCs being the likely first candidates for the node.

TSMC details that N5 currently is progressing with defect densities one quarter ahead of N7, with the new node having better yields at the time of mass production than both their predecessor major nodes N7 and N10, with a projected defect density that’s supposed to continue to improve past the historic trends of the last two generations.

The foundry is preparing a new N5P node that’s based on the current N5 process that extends its performance and power efficiency with a 5% speed gain and a 10% power reduction.

Beyond N5P, TSMC is also introducing the N4 node that represents a further evolution from the N5 process, employing further EUV layers to reduce masks, with minimal migration work required by chip designers. We’ll be seeing N4 risk production start in 4Q21 for volume production later in 2022.

Today’s biggest news was TSMC’s disclosure on their next big leap past the N5 process node generation family, which is the 3nm N3 node. We’ve heard that TSMC had been working on defining the node back last year with progress going well.

Contrary to Samsung’s 3nm process node which makes use of GAA (Gate-all-around) transistor structures, TSMC will instead be sticking with FinFET transistors and relying on “innovative features” to enable them to achieve the full-node scaling that N3 promises to bring.

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
  TSMC
N7
vs
16FF+
N7
vs
N10
N7P
vs
N7
N7+
vs
N7
N5
vs
N7
N5P
vs
N5
N3
vs
N5
Power -60% <-40% -10% -15% -30% -10% -25-30%
Performance +30% ? +7% +10% +15% +5% +10-15%
Logic Area

Reduction %

(Density)


70%


>37%


-


~17%
0.55x

-45%

(1.8x)


-
0.58x

-42%

(1.7x)
Volume
Manufacturing

 

 

 
Q2 2019
 
Q2 2020 2021 H2 2022

Compared to it’s N5 node, N3 promises to improve performance by 10-15% at the same power levels, or reduce power by 25-30% at the same transistor speeds. Furthermore, TSMC promises a logic area density improvement of 1.7x, meaning that we’ll see a 0.58x scaling factor between N5 and N3 logic. This aggressive shrink doesn’t directly translate to all structures, as SRAM density is disclosed at only getting a 20% improvement which would mean a 0.8x scaling factor, and analog structures scaling even worse at 1.1x the density.

Modern chip designs are very SRAM-heavy with a rule-of-thumb ratio of 70/30 SRAM to logic ratio, so on a chip level the expected die shrink would only be ~26% or less.

N3 is planned to enter risk production in 2021 and enter volume production in 2H22. TSMC’s disclosed process characteristics on N3 would track closely with Samsung’s disclosures on 3GAE in terms of power and performance, but would lead more considerably in terms of density.

We’ll be posting more detailed content from TSMC’s Technology Symposium in due course, so please stay tuned for more information and updates.

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  • yankeeDDL - Tuesday, August 25, 2020 - link

    30% power reduction and 1.8x density is quite decent, in my opinion. Reply
  • psychobriggsy - Tuesday, August 25, 2020 - link

    It appears like you've been reading the Intel presentations.

    The reality is that Marvell have shown a 40% average density improvement, and 40% power savings (at iso-performance) from N5 compared to N7- https://semiaccurate.com/2020/08/25/marvell-talks-...

    Analogue and I/O always scales poorly - it's why as we enter a chiplet age, these are on older processes.

    N3's poor SRAM scaling is likely going to result in SRAM moving to another die that is 3D assembled via TSVs to the dense logic die.
    Reply
  • cb88 - Tuesday, August 25, 2020 - link

    The advantage would be increased fab throughput.... since some of the quad and double patterning is eliminated in favor of EUV... they can churn out a LOT more chips. Probably 2.5x as many transistors produced per unity time even though the density increase isn't that much. Reply
  • Spunjji - Wednesday, August 26, 2020 - link

    Useless comment as ever, Gondalf. The contradictory information is just a few inches above your comment. Reply
  • eek2121 - Monday, August 24, 2020 - link

    Well no, Zen 4 is currently scheduled for a 2021 release. Reply
  • nandnandnand - Monday, August 24, 2020 - link

    Zen 3+ "Warhol" in 2021, in between Zen 3 "Vermeer" and Zen 4 "Raphael". Reply
  • scineram - Tuesday, August 25, 2020 - link

    Well no, it's not. Reply
  • MarcusMo - Monday, August 24, 2020 - link

    Crazy to think that the battle for the performance crown in the next couple of years will likely be fought by AMD and Apple... Reply
  • Azix - Monday, August 24, 2020 - link

    How do you figure? If you mean on the extra high core count level, sure. core for core though, you'd have to limit it to performance/watt for AMD to come out ahead of intel. Reply
  • michael2k - Monday, August 24, 2020 - link

    Maybe they mean AMD and Apple on 3nm vs Intel on 7nm? Reply

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