We’ve known about Intel’s Cooper Lake platform for a number of quarters. What was initially planned, as far as we understand, as a custom silicon variant of Cascade Lake for its high-profile customers, it was subsequently productized and aimed to be inserted into a delay in Intel’s roadmap caused by the development of 10nm for Xeon. Set to be a full range update to the product stack, in the last quarter, Intel declared that its Cooper Lake platform would end up solely in the hands of its priority customers, only as a quad-socket or higher platform. Today, Intel launches Cooper Lake, and confirms that Ice Lake is set to come out later this year, aimed at the 1P/2P markets.

Count Your Coopers: BFloat16 Support

Cooper Lake Xeon Scalable is officially designated as Intel’s 3rd Generation of Xeon Scalable for high-socket count servers. Ice Lake Xeon Scalable, when it launches later this year, will also be called 3rd Generation of Xeon Scalable, except for low core count servers.

For Cooper Lake, Intel has made three key additions to the platform. First is the addition of AVX512-based BF16 instructions, allowing users to take advantage of the BF16 number format. A number of key AI workloads, typically done in FP32 or FP16, can now be performed in BF16 to get almost the same throughput as FP16 for almost the same range of FP32. Facebook made a big deal about BF16 in its presentation last year at Hot Chips, where it forms a critical part of its Zion platform. At the time the presentation was made, there was no CPU on the market that supported BF16, which led to this amusing exchange at the conference:

BF16 (bfloat16) is a way of encoding a number in binary that attempts to take advantage of the range of a 32-bit number, but in a 16-bit format such that double the compute can be packed into the same number of bits. The simple table looks a bit like this:

Data Type Representations
Type Bits Exponent Fraction Precision Range Speed
float32 32 8 23 High High Slow
float16 16 5 10 Low Low 2x Fast
bfloat16 16 8 7 Lower High 2x Fast

By using BF16 numbers rather than FP32 numbers, it would also mean that memory bandwidth requirements as well as system-to-system network requirements could be halved. On the scale of a Facebook, or an Amazon, or a Tencent, this would appeal to them. At the time of the presentation at Hot Chips last year, Facebook confirmed that it already had silicon working on its datasets.

Doubling Socket-to-Socket Interconnect Bandwidth

The second upgrade that Intel has made to Cooper Lake over Cascade Lake is in socket-to-socket interconnect. Traditionally Intel’s Xeon processors have relied on a form of QPI/UPI (Ultra Path Interconnect) in order to connect multiple CPUs together to act as one system. In Cascade Lake Xeon Scalable, the top end processors each had three UPI links running at 10.4 GT/s. For Cooper Lake, we have six UPI links also running at 10.4 GT/s, however these links still only have three controllers behind them such that each CPU can only connect to three other CPUs, but the bandwidth can be doubled.

This means that in Cooper Lake, each CPU-to-CPU connection involves two UPI links, each running at 10.4 GT/s, for a total of 20.8 GT/s. Because the number of links is doubled, rather than an evolution of the standard, there are no power efficiency improvements beyond anything Intel has done to the manufacturing process. Note that double the bandwidth between sockets is still a good thing, even if latency and power per bit is still the same.

Intel still uses the double pinwheel topology for its eight socket designs, ensuring at max two hops to any required processor in the set. Eight socket is the limit with a glueless network – we have already seen companies like Microsoft build servers with 32 sockets using additional glue logic.

Memory and 2nd Gen Optane

The third upgrade for Cooper Lake is the memory support. Intel is now supporting DDR4-3200 with the Cooper Xeon Platinum parts, however only in a 1 DIMM per channel (1 DPC) scenario. 2 DPC is supported, but only at DDR4-2933. Support for DDR4-3200 technically gives the system a boost from 23.46 GB/s per channel to 25.60 GB/s, an increase of 9.1%.

The base models of Cooper Lake will also be updated to support 1.125 TiB of memory, up from 1 TB. This allows for a 12 DIMM scenario where six modules are 64 GB and six modules are 128 GB. One of the complaints about Cascade Xeons was that in 1 TB mode, it would not allow for an even capacity per memory channel when it was filled with memory, so Intel have rectified this situation. In this scenario, it means that the six 128 GB modules could also be Optane. Why Intel didn’t go for the full 12 * 128 GB scenario, we’ll never know.

The higher memory capacity processors will support 4.5 TB of memory, and be listed as ‘HL’ processors.

Cooper Lake will also support Intel’s second generation 200-series Optane DC Persistent Memory, codenamed Barlow Pass. 200-series Optane DCPMM will still available in 128 GB, 256 GB, and 512 GB modules, same as the first generation, and will also run at the same DDR4-2666 memory speed. Intel claims that this new generation of Optane offers 25% higher memory bandwidth than the previous generation, which we assume comes down to a new generation of Optane controller on the memory and software optimization at the system level.

Intel states that the 25% performance increase is when they compare 1st gen Optane DCPMM to 2nd gen Optane DCPMM at 15 W, both operating at DDR4-2666. Note that the first-gen could operate in different power modes, from 12 W up to 18 W. We asked Intel if the second generation was the same, and they stated that 15 W is the maximum power mode offered in the new generation.

Socket, Silicon, and SKUs
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  • Deicidium369 - Saturday, June 20, 2020 - link

    Find one motherboard that is more than 2 sockets for AMD. Just 1. Reply
  • azfacea - Thursday, June 18, 2020 - link

    i was kind of suspicious epyc 4 socket might not exist when i said that, but still i dont think it makes much of difference if you need commodity x86 compute, just buy two servers. it will still take less space and be more power efficient as long as its TSMC 7nm vs intel 14nm++

    what would make a difference is: max memory. if there is a server from intel that has double the max memory than biggest from AMD, then i guess there would be niche. but if such a customer exists surly AMD can rectify that if they simply choose to.
    Reply
  • schujj07 - Thursday, June 18, 2020 - link

    Unless you are using Optane DIMMs, Xeon cannot compete with AMD in terms of RAM capacity. For non Optane Xeon you would need a 4 socket host to surpass what Epyc can do in a single socket. However, 256GB LRDIMMs are INSANELY expensive, ~$5000/DIMM. Even 128GB LRDIMMs are still $1100/DIMM minimum compared to $350/DIMM for 64GB RDIMMs.

    I can tell you from personal experience that running SAP HANA on Epyc does work, at least in a virtualized environment. It will even pass the SAP HANA PRD Performance test. Despite what SAP, probably Intel as well, says, you do not need Xeon to run HANA. The 8 channel RAM makes things a lot nicer in getting enough RAM for multiple HANA DBs or one massive DB as well.
    Reply
  • kc77 - Thursday, June 18, 2020 - link

    Not to mention to use Optane you actually have to have your software written/configured around it. You can't just slap it in and experience wonderful performance. Reply
  • schujj07 - Thursday, June 18, 2020 - link

    I've never used Optane, but I do know that VMware has 2 different modes for it.
    https://blogs.vmware.com/vsphere/2019/04/announcin...
    I don't know what the performance will be if the software isn't written for it, but hopefully the hypervisor can at least help.
    Reply
  • Zibi - Thursday, June 18, 2020 - link

    Optane persistent memory is kinda non feature in the Vmware world. Yes you can use it, you can pass it as either very fast disk or pmem dev to the VMs that understands this, but you lose HA with that. There is no mechanism to protect (replicate) Optane mem content in case of the node failure.
    For me the only viable scenario for Optane persistent memory is the cache layer in the SDS.
    Reply
  • Deicidium369 - Thursday, June 18, 2020 - link

    I have been told it was not a big lift to get accomplished. SAP already has been shipping with Optane DIMM support - we can move to Optane DIMMs with our SAP install if we want. Our install is small in comparison to the systems and installs at Fortune companies.

    Pretty sure Oracle support is already baked in as well.
    Reply
  • Deicidium369 - Thursday, June 18, 2020 - link

    The advantages to using Intel on SAP HANA will be the reduced boot times when Optane DIMMs are used. Reply
  • Zibi - Thursday, June 18, 2020 - link

    You are aware though that the disadvantage will be worse memory performance in any other operations ? Optane DIMMs have worse throughput and worse latency. I don't know how often SAP HANA environments are restarted. I'd be surprised if that would be more than once per quarter. Reply
  • JayNor - Thursday, June 18, 2020 - link

    Worse performance than the database not fitting in memory? I don't think so... Reply

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