Back in November last year, we reported that SK Hynix had developed and deployed its first DDR5 DRAM. Fast forward to the present, and we also know SK Hynix has recently been working on its DDR5-6400 DRAM, but today the company has showcased that it has plans to offer up to DDR5-8400, with on-die ECC, and an operating voltage of just 1.1 Volts.

WIth CPU core counts rising with the fierce battle ongoing between Intel and AMD in the desktop, professional, and now mobile markets, the demand to increase throughput performance is high on the agenda. Memory bandwidth by comparison has not been increasing as much, and at some level the beast needs to be fed. Announcing more technical details on its official website, SK Hynix has been working diligently on perfecting its DDR5 chips with capacity for up to 64 Gb per chip.

SK Hynix had previously been working on its DDR5-6400 DRAM, which has 16 Gb which is formed of 32 banks, with 8 bank groups, with double the available bandwidth and access potential when compared with DDR4-3200 memory. For reference, DDR4 uses 16 banks with 4 bank groups. The key solution to improve access throughout is the burst length, which has been doubled to 16 when compared with 8 on DDR4. Another element to consider is DDR4 can't by proxy run operations while it's refreshing. DDR5 is using SBRF (same bank refresh function) which allows the system the ability to use other banks while one is refreshing, which in theory improves memory access availability.

As we've already mentioned, SK Hynix already has DDR5-6400 in its sights which are built upon its second-generation 10nm class fabrication node. SK Hynix has now listed that it plans to develop up to DDR5-8400. Similar in methodology to its DDR5-6400 DRAM, DDR5-8400 requires much more forethought and application. What's interesting about SK Hynix's DDR5-8400 is the jump in memory banks, with DDR5-8400 using 32 banks, with 8 bank groups.

Not just content at increasing overall memory bandwidth and access performance over DDR4, the new DDR5 will run with an operating voltage of 1.1 V. This marks a 9% reduction versus DDR4's operating voltage which is designed to make DDR5 more power-efficient, with SK Hynix reporting that it aims to reduce power consumption per bandwidth by over 20% over DDR4.

To improve performance and increase reliability in server scenarios, DDR5-8400 will use on-die ECC (Error Correction) and ECS (Error Check and Scrub) which is a milestone in the production of DDR5. This is expected to reduce overall costs, with ECS recording any defects present and sends the error count to the host. This is designed to improve transparency with the aim of providing enhanced reliability and serviceability within a server system. Also integrated into the design of the DDR5-8400 DRAM is Decision Feedback Equalization (DFE), which is designed to eliminate reflective noise when running at high speeds. SK Hynix notes that this increases the speed per pin by a large amount.

In the above image from specification comparison between DDR4 and DDR5 from SK Hynix, one interesting thing to note is that it mentions DRAM chips with density up to 64 gigabit. We already know that the chip size of DDR5 is 65.22mm², with a data rate of 6.4 Gbps per pin, and uses its 1y-nm 4-metal DRAM manufacturing process. It is worth pointing out that the DDR5-5200 RDIMM we reported on back in November 18, uses 16 Gb DRAM chips, with further scope to 32 Gb reported. SK Hynix aims to double this to 64 Gb chips which do double the density, at lower power with 1.1 volts.  

Head of DRAM Product Planning at SK Hynix, Sungsoo Ryu stated that:

"In the 4th Industrial Revolution, which is represented by 5G, autonomous vehicle, AI, augmented reality (AR), virtual reality (VR), big data, and other applications, DDR5 DRAM can be utilized for next-gen high-performance computing and AI-based data analysis".

SK Hynix if still on schedule with the current Coronavirus COVID-19 pandemic, looks set to enter mass production of DDR5 later this year.

Related Reading

Source: SK Hynix

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  • mode_13h - Sunday, April 5, 2020 - link

    > Does this mean that (almost?) all DDR5 will be ECC by default?

    You wish. ...but I doubt.

    > I'll be looking forward to the ability to load up ... with 8x64 GB modules

    Whatchu gonna do with all that RAM? ...all that RAM? ...all that RAM?
    Reply
  • Mikewind Dale - Sunday, April 5, 2020 - link

    I've been learning a new statistical technique that requires generating a 100,000 by 100,000 matrix of 64 bit doubles. Just that matrix by itself is about 80 GB. And it's only an input into a statistical computation that is estimated with quad precision. I tried to run the computation and got an error that Windows tried but failed to allocate 200 GB of memory. Reply
  • mode_13h - Monday, April 6, 2020 - link

    LOL. Ouch.

    It feels like you need something other than brute force, though. The obvious first question would be whether you tried virtual memory, on a fast NVMe SSD. Also, try a matrix library designed to use coherent access patterns.
    Reply
  • willis936 - Monday, April 6, 2020 - link

    Are you part of a research group? If so, you should float thenuse of supercomputer time to your group. Reply
  • mode_13h - Tuesday, April 7, 2020 - link

    If he could access a supercomputer that easily, do you seriously think he'd be planning on building a new workstation to run his program?

    That said, maybe some cloud instances have that much RAM. It'd be worth looking into.
    Reply
  • eastcoast_pete - Monday, April 6, 2020 - link

    So, do they have a working sample of their DDR5-8400 DRAM?
    Also, what about other memory makers like Samsung or Micron? Any word on their plans or working samples?
    Reply

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